The present invention is directed, in general, to digital filters capable of resource sharing, and, more specifically, to a digital filter capable of adapting filter cells according to the standard of the received signal.
Modern communication devices, including both wireless and wireline devices, often rely on advanced digital signal processing technology to receive and demodulate digital signals that are transmitted through, and distorted by, a dispersive channel, such as the atmosphere or cabling. An important component in many of these communication devices is the digital filter. Conventional digital filters are comprised of a series arrangement of delay elements, or taps, into which a series of digital samples are fed. Each tap contains a data register that holds a data sample, a coefficient register that stores a coefficient, and a multiplier that multiplies the data sample by the coefficient. The outputs of all of the multipliers are then added together in a summation circuit to form the filter output. Thus, digital filters are based on a filter core that is implemented by multiple replications and daisy chaining of the same basic filter cell.
Different types of filters are used for different types of digital signals, usually because of the need for a different number of filter cells. Thus, the structure of a digital filter used to filter quadrature amplitude modulated (QAM) signals, such as a 64 QAM signal, is different than the structure of a digital filter used to filter a pulse amplitude modulated (PAM) signal, such as an eight vestigial side band (8 VSB) signal. In general, as the complexity of the function performed by a digital filter increases, so too does the number of cells in the digital filter increase. The corresponding increase in the size of the filter becomes a severe disadvantage in integrated circuits or other systems in which the space available is limited.
To reduce the size of digital filters that employ a large number of cells, resource-sharing techniques are frequently used. Typically, resource sharing is implemented by using the same multiplier to multiply the data samples and coefficients from different taps. Since multipliers are frequently the largest component found in filter cells, sharing a multiplier among a plurality of taps greatly reduces the size of a digital filter. When a filter cell is implemented with resource sharing for multiple taps, it operates with a clock frequency that is multiple times higher than the data sampling frequency at the filter input.
There is still much room for improvement, however, with respect to resource sharing. This is particularly true in multimode digital filters that are capable of operating in different modes to filter signals of different modulation types, such as 64 QAM and 8 VSB signals. In a 64 QAM mode, the digital signal samples at the filter input and the filter coefficients are complex values consisting of real and imaginary components. In an 8VSB mode, the digital signal samples at the filter input and the filter coefficients are real values, but the symbol rate is twice as high for the same channel capacity and bandwidth utilization. Conventional multimode filters are implemented with separate circuitry for each mode, with little, if any, resource sharing.
There is therefore a need in the art for improved digital filter designs. In particular, there is a need in the art for digital filter designs that implement resource sharing to the greatest extent possible. More particularly, there is a need for improved multimode digital filters that implement resource sharing in the circuitry used for each mode of the digital filter.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide, for use in a digital filter, a digital filter cell capable of processing in a first mode a first signal having real data components only and processing in a second mode a second signal having real data components and imaginary data components. In an advantageous embodiment of the present invention, the digital filter cell comprises: 1) a plurality of serially coupled coefficient registers capable of receiving a sequence of coefficients; 2) a plurality of serially coupled data registers capable of receiving a sequence of digital data samples, each of the serially coupled data registers having a tap output; 3) a data multiplexer having a plurality of input channels, each of the input channels capable of receiving the tap output from each of the plurality of serially coupled data registers; and 4) a product summation circuit having a first input coupled to an output of the data multiplexer and a second input coupled to an output of a selected one of the plurality of serially coupled coefficient registers, wherein the product summation circuit is capable of generating a summation of a plurality of products formed by sequentially multiplying each coefficient received from the selected coefficient register by a corresponding digital data sample received from a selected one of the plurality of serially coupled data registers, wherein the product summation circuit adds each of the plurality of products to the summation when the digital filter cell is operating in the first mode and wherein the product summation circuit one of 1) selectively adds ones of the plurality of products to the summation and 2) selectively subtracts ones of the plurality of products from the summation when the digital filter cell is operating in the second mode.
According to one embodiment of the present invention, the product summation circuit comprises a conditional minus one multiplier capable of selectively inverting a value of a data sample received from the data multiplexer, a multiplier, an adder and an accumulator register.
According to another embodiment of the present invention, the product summation circuit comprises a multiplier, an adder-subtractor, and an accumulator register.
According to still another embodiment of the present invention, the first mode comprises an eight vestigial side band (8 VSB) mode of operation.
According to yet another embodiment of the present invention, the second mode of operation comprises a quadrature amplitude modulation (QAM) mode of operation.
According to a further embodiment of the present invention, the real data in the first mode are sampled at a frequency of 2F and the real data components and imaginary data components in the second data mode are sampled at a frequency of F.
According to a still further embodiment of the present invention, the digital filter is adaptive and the coefficients are modifiable.
According to a yet further embodiment of the present invention, the digital filter cell further comprises a coefficient update circuit having a first input coupled to an output of a first selected one of the plurality of serially coupled coefficient registers, a second input coupled to a second digital filter cell in the digital filter, and an output coupled to an input of a second selected one of the plurality of serially coupled coefficient registers.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand THE DETAILED DESCRIPTION OF THE INVENTION that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprisexe2x80x9d and derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontroller,xe2x80x9d xe2x80x9cprocessor,xe2x80x9d or xe2x80x9capparatusxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.